VSC880 查看數據表（PDF） - Vitesse Semiconductor

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VSC880

High Performance 16x16 Serial Crosspoint Switch

Vitesse Semiconductor 

Data Sheet

VSC880

VITESSE

SEMICONDUCTOR CORPORATION

High Performance 16x16

Serial Crosspoint Switch

Pin

RESYNEN

INT

MEN

FACLPBK

CMODE

TESTEN

SCANIN

SCANOUT

WCLK

REFCLK

TCLKEN

CCLK

RESET

BSTLPBK

BSTEN

BSTRST

BSTPASS

Name

I/O

Freq

Type

Description

Resynch Enable

I

<1MHz

TTL

If RESYNEN is HIGH, all links that have a link error

condition will be reinitialized. This will override the internal

control register settings.

Interrupt

O

<1MHz

TTL

If INT is LOW, a receive error has occurred in one of the

links that has it’s output enable (OE) bit set HIGH and

interrupt control register bit set HIGH.

Reserved

I

<1MHz This signal is reserved for future use and should be set LOW

TTL during normal operation.

Facility Loop Back

I

<1MHz

TTL

If this signal is set HIGH, all serial inputs are looped back to

their serial outputs. This will override the internal control

register setting.

Cell Mode

I

<1MHz

TTL

CMODE is set HIGH for Cell Mode operation.

Scan Test Enable

I

<1MHz

TTL

This signal is used in ATE testing to measure propagation

delay. It is also used in ATE testing of the BIST logic. Set to

logic LOW in normal operation.

Scan Data In

I

62.5Mb/s The input signal for measuring propagation delay on the

TTL ATE tester.

Scan Data Out

O

62.5Mb/s

TTL

The output signal for measuring propagation delay on the

ATE tester. When TESTEN is set LOW, the longer delay

path is enabled.

Word Clock

O

62.5MHz

TTL

This is the word clock output.

Reference Clock

I

62.5MHz This is the reference clock and the source of the system wide

TTL word clock period.

Test Clock Enable

I

<1MHz

TTL

This input is set HIGH in test mode, so that the CMU is

bypassed and the REFCLK becomes the bit clock. This

signal is for ATE test only. Set LOW in normal operation.

Cell Clock

This is the source of the system wide cell clock. It is

I

62.5MHz internally synchronized to the REFCLK. In Packet mode, set

TTL this signal HIGH to enable external switch configuration for

BIST.

Reset

I

<1MHz

TTL

Global chip reset (active LOW)

When BSTLPBK is set HIGH and TESTEN is LOW, all

Built-in Self Test Loop

Back

I

<1MHz serial data output signals are looped back to their serial data

TTL inputs. If BSTLPBK is set HIGH and TESTEN is HIGH,

only ports 0-7 are placed in loopback.

Built-in Self Test Enable I

<1MHz When BSTEN is HIGH, at-speed built-in self testing is

TTL enabled.

Built-in Self Test Reset

I

<1MHz The BSTRST signal is set HIGH to reset the PRBS

TTL generator and comparator.

Built-in Self Test Pass

O

<1MHz

TTL

The BSTPASS signal is HIGH if BTSEN is HIGH and the

PRBS comparator detects the correct pattern in built-in self

test mode.

G52191-0, Rev 4.2

01/05/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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