VSC880 查看數據表（PDF） - Vitesse Semiconductor
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VSC880 Datasheet PDF : 28 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
High Performance 16x16
Serial Crosspoint Switch
Data Sheet
VSC880
1.1.6 Link Error Detection
There are four types of link errors that can be flagged on the receive serial links. Link errors are detected using
IDLE words. If a link error is detected, a bit in the LERR register is set HIGH for that particular channel (see section
1.4). After every 8 link errors, a bit in the TERR register is set HIGH. If the DRU goes out of range, a bit in the DERR
register is set HIGH. If the last word in the cell period is an IDLE word and it does not have bits B[1:0] set HIGH to
designate a cell clock, a bit in the CERR register will be set HIGH. If an error bit is set in any of these registers, the
INT signal can be programmed to go LOW and/or the link can be programmed to automatically start link
initialization depending on the value loaded into the Interrupt Control Register (see section 1.4). These error register
bits will be cleared if the link is reinitialized, or the registers are read. If the signal RESYNEN is set HIGH, link
initialization will begin immediately upon the detection of any of these errors. If the switch is used without IDLE
words, the user is responsible for detecting parity error conditions and restarting the link initialization process.
1.2 Data Encoding Format
To provide self-routing and cell synchronization, the transceiver and switch require special word formats.
Depending on the mode that the switch is used in, different word types are recognized by the switch. In both the
Packet and Cell Modes, the switch processes both data words and command words. They have the same format in
both modes and will be described in following section. The format for the connection request words and header
words are described later in the Packet Mode section.
1.2.1 Data Word Format on the Serial Data Lines
The data word format as seen at the serial output of the transceiver or switch chip is shown below. Two overhead
bits are added by the transceiver or switch chip to designate a data word to the receiving switch chip or transceiver.
The serial data is transmitted with the MSB first.
33 32
BB
10
31 30 29 28
DDDD
31 30 29 28
27 26 25 24
DDDD
27 26 25 24
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08
DDDD
23 22 21 20
DDDD
19 18 17 16
DDDD
15 14 13 12
DDDD
11 10 09 08
--------------- Data Payload ----------------
07 06 05 04
DDDD
07 06 05 04
Where:
B[1:0]If Packet Mode,
01=Flow control channel,
10=Flow control channel,
11=Acknowledge from switch chip or header word to switch chip
If Cell Mode, 01, 10, 11 = data
D[31:0]32 bit data payload
03 02 01 00
DDDD
03 02 01 00
1.2.2 Command Word Format on the Serial Data Lines
The command word format as seen at the serial output of the transceiver or switch chip is shown below. Two
overhead bits are added by the transceiver or switch to designate a command word (00) to the receiving switch chip or
transceiver. The serial data is transmitted with the MSB first. In Packet Mode, the IDLE word from the switch always
returns the current output connections for the port.
Page 6
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52191-0, Rev 4.2
01/05/01
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