VSC880TY 查看數據表（PDF） - Vitesse Semiconductor

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VSC880TY

High Performance 16x16 Serial Crosspoint Switch

Vitesse Semiconductor 

Data Sheet

VSC880

VITESSE

SEMICONDUCTOR CORPORATION

High Performance 16x16

Serial Crosspoint Switch

ADDR[5:0] R/W 7

0 1 0 0 1 1 R/W

101100 R

101101 R

101110 R

101111 R

110000 R

110001 R

110010 R

110011 R

X 1 0 1 0 0 R/W

X 1 0 1 0 1 R/W

X 1 0 1 1 0 R/W

X 1 0 1 1 1 R/W

X 1 1 0 0 0 R/W

X 1 1 0 0 1 R/W

X 1 1 0 1 0 R/W

X 1 1 0 1 1 R/W

CDATA[7:0] Bit Position

6

5

4

3

2

1

C7[3:0]

S0[3:0]

S1[3:0]

S2[3:0]

S3[3:0]

S4[3:0]

S5[3:0]

S6[3:0]

S7[3:0]

FI[7:0]

FI[15:8]

RSY[7:0]

RSY[15:8]

OE[7:0]

OE[15:8]

LPBK[7:0]

LPBK[15:8]

C15[3:0]

S8[3:0]

S9[3:0]

S10[3:0]

S11[3:0]

S12[3:0]

S13[3:0]

S14[3:0]

S15[3:0]

0

Output7/Output15 Config

Output0/Output8 Status

Output1/Output9 Status

Output2/Output10 Status

Output3/Output11 Status

Output4/Output12 Status

Output5/Output13 Status

Output6/Output14 Status

Output7/Output15 Status

Force IDLEs LSB

Force IDLEs MSB

Resynch LSB

Resynch MSB

Output Enable LSB

Output Enable MSB

Loopback LSB

Loopback MSB

Where:

CE Cell clock errorRCE

Resynch on cell errorICE

Interrupt on cell error

DE DRU error RDE

Resynch on DRU errorIDE

Interrupt on DRU error

TE Threshold errorRTE

Resynch on thresh errorITE

Interrupt on threshold error

LE Link error RLE

Resynch on link errorILE

Interrupt on link error

BIST

Set this bit HIGH to test the BIST circuitry

CDEL[3:0]

Cell clock delay

CERR[15:0]Cell clock error register, bit 0 is channel 0 etc, Cleared on read

DERR[15:0]DRU error register, bit 0 is channel 0 etc. Cleared on read

TERR[15:0]Threshold error register, bit 0 is channel 0 etc. Cleared on read

LERR[15:0]Link error register, bit 0 is channel 0 etc, Cleared on read

CN[3:0]Switch configuration data. N is the output port number, [3:0] is the input port connected. Default = 0xF.

SN[3:0]Output status data. N is the output port number, SN[3:2] = 00 for normal operation.

01 for out of synch

10 for word synch in progress

11 for cell synch in progress

SN[1] = Output busy in packet mode

SN[0] = Connection valid in packet mode

G52191-0, Rev 4.2

01/05/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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