VSC8111QB 查看數據表（PDF） - Vitesse Semiconductor
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VSC8111QB
Vitesse Semiconductor
VSC8111QB Datasheet PDF : 26 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Figure 9: Receive Data Output Timing Diagram
RXCLKIN+
RXCLKIN-
RXLSCKOUT
TRXCLKIN
TRXLSCK
Data Sheet
VSC8111
RXOUT [7:0]
FP
A1
A2
A2
A2
A2
TRXVALID
Table 8: Receive Data Output Timing Table (STS-12 Operation)
Parameter
Description
Min
TRXCLKIN Receive clock period
-
TRXLSCK
Receive data output byte clock period
-
TRXVALID
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
4.0
TPW
Pulse width of frame detection pulse FP
-
Table 9: Receive Data Output Timing Table (STS-3 Operation)
Parameter
Description
Min
TRXCLKIN Receive clock period
-
TRXLSCKT Receive data output byte clock period
-
TRXVALID
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
22
TPW
Pulse width of frame detection pulse FP
-
Typ
1.608
12.86
-
12.86
Max
-
-
-
-
Typ
6.43
51.44
-
51.44
Max
-
-
-
-
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns
Page 10
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52142-0, Rev 4.2
8/31/98
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