VSC8111 查看數據表（PDF） - Vitesse Semiconductor

零件编号

产品描述 (功能)

生产厂家

VSC8111

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Data Sheet

VSC8111

Table 3: Clock Multiplier Unit Performance

Name

RCd

RCj

RCj

RCj

RCj

RCf

OCj

OCj

OCj

OCj

OCfrange

OCd

Description

Reference clock duty cycle

Reference clock jitter (RMS) @ 77.76 MHz ref (1)

Reference clock jitter (RMS) @ 51.84 MHz ref (1)

Reference clock jitter (RMS) @ 38.88 MHz ref (1)

Reference clock jitter (RMS) @ 19.44 MHz ref (1)

Reference clock frequency tolerance (2)

Output clock jitter (RMS) @ 77.76 MHz ref (3)

Output clock jitter (RMS) @ 51.84 MHz ref (3)

Output clock jitter (RMS) @ 38.88 MHz ref (3)

Output clock jitter (RMS) @ 19.44 MHz ref (3)

Output frequency

Output clock duty cycle

Min

Typ

Max

Units

40

60

%

13

ps

12

ps

9

ps

5

ps

-20

+20

ppm

8

ps

10

ps

13

ps

15

ps

620

624

MHz

40

60

%

(1) These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements

(< 10 mUIrms)

(2) Needed to meet SONET output frequency stability requirements

(3) Measured

Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.

AC Timing Characteristics

RXCLKIN+

RXCLKIN-

RXDATAIN+

RXDATAIN-

Figure 7: Receive High Speed Data Input Timing Diagram

TRXCLK

TRXSU

TRXH

Table 4: Receive High Speed Data Input Timing Table (STS-12 Operation)

Parameter

TRXCLK

TRXSU

TRXH

Description

Receive clock period

Serial data setup time with respect to RXCLKIN

Serial data hold time with respect to RXCLKIN

Min

Typ

-

1.608

250

-

250

-

Max

-

-

-

Units

ns

ps

ps

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52142-0, Rev 4.2

8/31/98

Share Link: