VSC8111QB 查看數據表（PDF） - Vitesse Semiconductor
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VSC8111QB
Vitesse Semiconductor
VSC8111QB Datasheet PDF : 26 Pages
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Data Sheet
VSC8111
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Table 5: Receive High Speed Data Input Timing Table (STS-3 Operation)
Parameter
TRXCLK
TRXSU
TRXH
Description
Receive clock period
Serial data setup time with respect to RXCLKIN
Serial data hold time with respect to RXCLKIN
Min
Typ
-
6.43
1.5
-
1.5
-
Figure 8: Transmit Data Input Timing Diagram
TPROP
TXLSCKOUT
TCLKIN
TXLSCKIN
TINSU
TINH
TXIN [7:0]
Max
-
-
-
Units
ns
ns
ns
Table 6: Transmit Data Input Timing Table (STS-12 Operation)
Parameter
Description
Min
TCLKIN
Transmit data input byte clock period
-
TINSU
Transmit data setup time with respect to TXLSCKIN
1.0
TINH
Transmit data hold time with respect to TXLSCKIN
1.0
TPROP
Maximum allowable propagation delay for connecting
TXLSCKOUT to TXLSCKIN
-
Table 7: Transmit Data Input Timing Table (STS-3 Operation)
Parameter
Description
Min
TCLKIN
Transmit data input byte clock period
-
TINSU
Transmit data setup time with respect to TXLSCKIN
1.0
TINH
Transmit data hold time with respect to TXLSCKIN
1.0
TPROP
Maximum allowable propagation delay for connecting
TXLSCKOUT to TXLSCKIN
-
Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case
Typ
12.86
-
-
-
Max
-
-
-
3.0
Typ
51.44
-
-
-
Max
-
-
-
30
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns
G52142-0, Rev 4.2
8/31/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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