VSC8114 查看數據表（PDF） - Vitesse Semiconductor

零件编号

产品描述 (功能)

生产厂家

VSC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC8114

detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel con-

verter. This only occurs when OOF is high. Both internal and external LOS functions are supported.

The VSC8114 provides the parity error detection and generation for the 8 bit data bus. On the receive side,

the parity of the 8 bit data outputs is generated. On the transmit side, the parity of the 8 bit data input is calcu-

lated and compared with the received parity input.

VSC8114 Block Diagram

EQULOOP

RESET

DQ

TXDATAOUT+/-

FACLOOP

1

QD

0

1

0

FRAMER

OOF

FP

0

1

1:8

DEMUX

Parity/

REG

8

RXOUT[7:0]

RXOUTP

0

Divide-by-8

1

Parity Chk

RXLSCKOUT

TXPERR

TXINP

8:1

MUX

REG

8

TXIN[7:0]

TXLSCKIN

Divide-by-8

TXLSCKOUT

10

LOOPTIM0

1

RXDATAIN+/-

0

CRUEQLP

RXCLKIN+/-

DSBLCRU

1

REC-DATA 0

CRU

REC-CLK 0

1

losdet

01

CMU

0

1

REFCLKP+/-

REFSEL

LOSPECL

LOSTTL

LOSDETEN_

CRUREFCLK

CRUREFSEL

Transmit Section

Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKIN.

See Figure 1. The data is then serialized (MSB leading) and presented to the TXDATAOUT+/- pins. The serial

output stream is synchronized to the CMU generated clock which is a phase locked and frequency scaled ver-

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

G52185-0, Rev 4.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

11/1/99

Share Link: