VSC8114 查看數據表（PDF） - Vitesse Semiconductor

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VSC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

Data Sheet

VSC8114

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Figure 6: External Integrator Capacitor

CP = 0.1 µF

CP1

CP2

+

-

CN1

CN2

CN = 0.1 µF

Table 1: Recommended External Capacitor Values

Reference

Frequency Divide Ratio

CP

CN

[MHz]

19.44

32

0.1

0.1

77.76

8

0.1

0.1

Type

X7R

X7R

Size

0603/0803

0603/0803

Tol.

+/-10%

+/-10%

Clock Recovery

The fully monolithic Clock Recovery Unit (CRU) consists of a Phase Detector, a Frequency Detector, a

Loop Filter and a Voltage Controlled Oscillator (VCO). The phase detector compares the phase information of

the incoming data with the recovered clock. The frequency detector compares the frequency component of the

data input with the recovered clock to provide the pull in energy during lock acquisition. The Loop Filter inte-

grates the phase information from the phase and frequency detectors and provides the control voltage to the

VCO.

Jitter Tolerance

Jitter Tolerance is the ability of the Clock Recovery Unit to track timing variations in the received data

stream. The Bellcore and ITU specifications allow the received optical data to contain jitter. The amount that

must be tolerated is a function of the frequency of the jitter. The CRU is designed to tolerate jitter with margin

over the specification limits, see Figure 7. The CRU obtains and maintains lock based on the data transition

information. When there is no transition on the data stream, the recovered clock frequency can drift. The

VSC8114 can maintain lock over 100 bits of no switching on the data stream.

G52185-0, Rev 4.0

11/1/99

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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