VSC8114QB1 查看數據表（PDF） - Vitesse Semiconductor

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VSC8114QB1

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

JITTER(UI P-P)

Figure 7: Jitter Tolerance

Data Sheet

VSC8114

150 Bellcore Requirement

15

1.5

0.15

VSC8114 Guaranteed

60

Jitter Tolerance

6

0.6

10

30

300

25K 250K 2.5M

JITTER FREQ(HZ)

Data Latency

The VSC8114 contains several operating modes, each of which exercise different logic paths through the

part. Table 2 bounds the data latency through each path with an associated clock signal.

Table 2: Data Latency

Circuit Mode

Description

Receive

Facilities

Loopback

MSB at RXDATAIN to data on RXOUT [7:0]

MSB at RXDATAIN to MSB at TXDATAOUT

Clock

Reference

RXCLKIN

RXCLKIN

Range of Clock

cycles

25-35

2-4

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

G52185-0, Rev 4.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

11/1/99

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