VSC8114 查看數據表（PDF） - Vitesse Semiconductor

零件编号

产品描述 (功能)

生产厂家

VSC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

Data Sheet

VSC8114

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

AC Timing Characteristics

RXCLKIN+

RXCLKIN-

RXDATAIN+

RXDATAIN-

Figure 8: Receive High Speed Data Input Timing Diagram

TRXCLK

TRXSU

TRXH

Table 3: Receive High Speed Data Input Timing Table

Parameter

TRXCLK

TRXSU

TRXH

Description

Receive clock period

Serial data setup time with respect to RXCLKIN

Serial data hold time with respect to RXCLKIN

Min

Typ

Max

Units

-

1.608

-

ns

250

-

-

ps

250

-

-

ps

RXCLKIN+

RXCLKIN-

RXLSCKOUT

Figure 9: Receive Data Output Timing Diagram

TRXCLKIN

TRXLSCK

RXOUT [7:0]

RXOUTP

FP

A1

A2

A2

A2

A2

TRXVALID

Table 4: Receive Data Output Timing Table

Parameter

Description

Min

Typ

Max

Units

TRXCLKIN Receive clock period

-

1.608

-

ns

TRXLSCK

Receive data output byte clock period

-

12.86

-

ns

TRXVALID

Time data on RXOUT [7:0], FP, and RXOUTP is valid

before and after the rising edge of RXLSCKOUT

4.0

-

-

ns

TPW

Pulse width of frame detection pulse FP

-

12.86

-

ns

G52185-0, Rev 4.0

11/1/99

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 9

Share Link: