VSC8116 查看數據表（PDF） - Vitesse Semiconductor

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VSC8116

ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Data Sheet

VSC8116

Functional Description

The VSC8116 is designed to provide a SONET/SDH compliant interface between the high speed optical

networks and the lower speed User Network Interface (UNI) devices such as the PM5355 S/UNI-622 (or

PM5312 STTX). The VSC8116 transmit section converts 8 bit parallel data at 77.76 Mb/s or 19.44 Mb/s to a

serial bit stream at 622.08 Mb/s or 155.52 Mb/s, respectively. It also provides a Facility Loopback function

which loops the received high speed data and clock directly to the transmit outputs. A Clock Multiplier Unit

(CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream

from input references frequency of 19.44 or 77.76 MHz. The CMU can be bypassed by using the receive clock

in loop timing mode thus synchronizing the entire part to a single clock (RXCLKIN).

The receive section provides the serial-to-parallel conversion, converting 155 Mb/s or 622 Mb/s to an 8 bit

parallel output at 19.44 Mb/s or 77.76 Mb/s, respectively. The receive section provides an Equipment Loopback

function which will loop the low speed transmit data and clock back through the receive section to the 8 bit par-

allel data bus and clock outputs. The receive section also contains a SONET/SDH frame detector circuit which

is used to provide frame recovery in the serial to parallel converter. The block diagram on page 1 shows the

major functional blocks associated with the VSC8116.

Transmit Section

Byte-wide data is presented to TXIN [7:0] and is clocked into the part on the rising edge of TXLSCKOUT

(refer to Figure 1). The data is then serialized (MSB leading) and presented at the TXDATAOUT+/- pins. The

serial output stream is synchronized to the CMU generated clock which is a phase locked and frequency scaled

version of the input reference clock. External control inputs CMUFREQSEL and STS12 select the multiply

ratio of the CMU and either STS-3 (155 Mb/s) or STS-12 (622 Mb/s) transmission (See Table 2).

Figure 1: Data and Clock Transmit Block Diagram

TXDATAOUT+

TXDATAOUT-

VSC8116

QD

QD

TXIN[7:0]

PM5355

QD

REFCLK

CMU

Divide-by-8

TXLSCKOUT

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

G52220-0, Rev 4.1

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

1/8/00

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