VSC8116QP1 查看數據表（PDF） - Vitesse Semiconductor

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VSC8116QP1

ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

Data Sheet

VSC8116

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Table 5: Receive High Speed Data Input Timing Table (STS-3 Operation)

Parameter

TRXCLK

TRXSU

TRXH

Description

Receive clock period

Serial data setup time with respect to RXCLKIN

Serial data hold time with respect to RXCLKIN

Min

Typ

-

6.43

1.5

-

1.5

-

Figure 8: Transmit Data Input Timing Diagram

Max

-

-

-

Units

ns

ns

ns

TXLSCKOUT

TXIN [7:0]

TCLKOUT

TINSU

TINH

Table 6: Transmit Data Input Timing Table (STS-12 Operation)

Parameter

Description

Min

Typ

Max

Units

TINSU

Transmit data setup time with respect to TXLSCKOUT

1.0

-

-

ns

TINH

Transmit data hold time with respect to TXLSCKOUT

1.0

-

-

ns

Table 7: Transmit Data Input Timing Table (STS-3 Operation)

Parameter

Description

Min

Typ

Max

Units

TINSU

Transmit data setup time with respect to TXLSCKOUT

1.0

-

-

ns

TINH

Transmit data hold time with respect to TXLSCKOUT

1.0

-

-

ns

Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case

G52220-0, Rev 4.1

1/8/00

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