VSC8124RE 查看數據表（PDF） - Vitesse Semiconductor

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VSC8124RE

2.488 Gb/s Quad Data Re-timer

Vitesse Semiconductor 

2.488 Gb/s Quad

Data Re-timer

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8124

Figure 2: Re-timed Serial Output Data Eye Diagram

Period

80%

20%

tr , tf

JG

Table 2: Serial Output Data Specification

Parameter

Description

Min

Typ

Max

Units

Conditions

JG

Jitter generation

-

JG

Jitter generation

-

JG

Jitter generation

-

tr, tf

Rise time, fall time

-

-

12ps rms

Normal Operation

-

15 ps rms

Fast Lock Mode

-

14ps rms

Within 40 µs after

REFCK phase

change

-

140

ps

20 to 80%

NOTES: 1) Jitter generation is measured at worst case power supply and temperature using 155.52 MHz clean reference clock

and clean serial data.

2) Jitter generation and rise, fall time specifications do not apply in re-timer bypass mode.

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52271-0, Rev. 1.14

2/23/00

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