VSC8124RE 查看數據表（PDF） - Vitesse Semiconductor

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VSC8124RE

2.488 Gb/s Quad Data Re-timer

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8124

2.488 Gb/s Quad

Data Re-timer

Figure 3: Fastlock Timing Diagram

Input Data Valid Data

Fastlock

Output Data Valid Data

200 Bit Times

1010...

80 Bit Times

Valid Data

200 Bit Times

Valid Data

Fast Lock

The VSC8124 supports a fastlock clock recovery mode which enables the clock recovery unit to lock the

retiming clock to the incoming data within 80 bit periods of initiation. As a requirement for the operation of the

fastlock function, the driving system must send a 0101 bit pattern while the fastlock pin is at a high logic level.

The FASTLOCK function is active simultaneously on all four data channels The fastlock pin has a TTL input

receiver meeting the specifications contained in Table 7. Note that jitter tolerance and re-timed data jitter are

degraded in FASTLOCK mode.

Loss of Signal

The loss of signal (LOS) circuitry is shared among four serial data channels, sampling the signal condition

on each channel sequentially. There is a loss of signal latch and active low indicator pin (LOS[0:3]N) for each

channel. In addition, there is an alarm pin (LOSALMN) which indicates the OR of the latched states of the four

channel indicators. The alarm pin uses an open drain output, so the alarm pins from multiple parts can be wired

together. A weak external pull resistor (approximately 1k Ohm) must be provided to utilize the wired NOR

alarm function. To facilitate system troubleshooting, the LOS latches can only be cleared by the active high

LOSCLR input.

The loss of signal clear (LOSCLR) input will cause all four loss of signal indicators LOS[0:3]N and the loss

of signal alarm (LOSALM) to be cleared. The LOSCLR input is asynchronous. It must be held active for at

least two reference clock cycles. A channel found to be missing after the error latch has been cleared, will again

set its error latch and the LOSALMN.

The LOS circuit examines a selected clock recovery channel for expected data transition activity. Expected

data activity includes pseudo-random data at a baud rate 16 times the reference clock frequency, and data

including at least 8500 consecutive bits of a 101010... pattern. The detector will allow the OC-48 framing pat-

tern to pass without triggering LOS. The LOS detector is disabled when FASTLOCK mode is active.

To assist diagnostic procedures, the effect of individual loss of signal indicators in the loss of signal alarm

can be masked. This is controlled by the MASK[0:3] pins. Each of those pins, when pulled high, disables the

effect of its respective channel on the loss of signal alarm (LOSALM). If all MASK pins are pulled high, the

LOSALM signal will not pull down. The loss of signal indicators for individual channels are not affected by the

MASK pins.

G52271-0, Rev. 1.14

2/23/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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