VSC8124RE 查看數據表（PDF） - Vitesse Semiconductor

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VSC8124RE

2.488 Gb/s Quad Data Re-timer

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

2.488 Gb/s Quad

Data Re-timer

Target Specification

VSC8124

Figure 7: Unused High Speed and REFCK Input Termination.

VCC

Quad data Re-timer

5.1 kΩ

DI

50Ω

VTERM

50Ω

DIN

5.1 kΩ

VEE

High Speed Specifications

Figure 8: Definition of I/O Levels

Vh

∆V

Vcm

Vl

NOTE: Diagram applies to all I/O swing specifications

Table 3: High Speed Driver Specification

Parameter

Description

Min

Typ

Max

Units

Conditions

∆V=(Vh - Vl)

Single ended peak-to-

peak

600

-

1000

mV

Terminated as in

Fig. 5 (DC Coupled)

VCM

Output common mode

1.8V

-

2.2

V

Terminated as in

Fig.5 (DC Coupled)

ZOUT

Ouput impedance

40

50

60

Ω

Measured Single-

ended

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52271-0, Rev. 1.14

2/23/00

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