VSC8140 查看數據表（PDF） - Vitesse Semiconductor

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VSC8140

2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Figure 15: Termination of Low-Speed LVPECL TXIN[15:0] Inputs

VCC

R1

ZO

CIN

R2

VEE

Chip Boundary

VCC = 3.3V

R1||R2 = Zo , R1 = 83Ω R2 =125Ω

VCCR2 + VEER1

R1+R2

= VBIAS

VREFIN

VREFOUT

VEE = 0V

CIN TYP = 100nF

for AC operation

Low-Speed Inputs

The incoming low-speed inputs are received by single-ended LVPECL inputs TXIN[15:0]. A reference

voltage is necessary to provide for optimal switching of the inputs. The user can either provide an input voltage

reference from the upstream device (VREFIN), or can use the reference voltage provided from the VSC8140

(VREFOUT). Side-by-side placement of the VREFIN and VREFOUT pins facilitates easy implementation.

For DC or AC operation, the external reference should have a nominal value equivalent to the common-

mode switch point of an LVPECL DC-coupled signal, and adhere to the DC characteristics as specified by the

Table 3 DC characteristics (VCM).

G52251-0, Rev. 4.0

9/6/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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