VSC8140QR 查看數據表（PDF） - Vitesse Semiconductor

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VSC8140QR

2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Data Sheet

VSC8140

Functional Description

Transmitter Low-Speed Interface

The Upstream Device should use the TXCLK16O as the timing source for its final output latch (see Figure

1). The Upstream Device should then generate a TXCLK16I that is phase-aligned with the data. The VSC8140

will latch TXIN[15:0]± on the rising edge of TXCLK16I+. The data must meet setup and hold times with

respect to TXCLK16I (see Table 1).

A FIFO exists within the VSC8140 to eliminate difficult system loop timing issues. Once the PLL has

locked to the reference clock, RESET must be held low for a minimum of five CLK16 cycles to initialize the

FIFO, then RESET should be set high and held constant for continuous FIFO operation. For the transparent

mode of operation (no FIFO), simply hold RESET at a constant low state (see Figure 2).

The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between

TXCLK16O and TXCLK16I. Once RESET is asserted and the FIFO initialized, the delay between TXCLK16O

and TXCLK16I can decrease or increase up to one period of the low-speed clock (6.4ns). Should this delay drift

exceed one period, the write pointer and the read pointer could point to the same word in the FIFO, resulting in

a loss of transmitted data (a FIFO overflow). In the event of a FIFO overflow, an active low OVERFLOW sig-

nal is asserted (for a minimum of five TXCLK16I cycles) which can be used to initiate a reset signal from an

external controller.

The TXCLK16O± output driver is a LVPECL output driver designed to drive a 50Ω transmission line. The

transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by

50Ω to VCC-2V on each line (see Figure 4). At any time, the equivalent split-end termination technique can be

substituted for the traditional 50Ω to VCC-2V on each line. AC-coupling can be achieved by a number of meth-

ods. Figure 5 illustrates an AC-coupling method for the occasion when the downstream device provides the bias

point for AC-coupling.

Figure 1: Low-Speed Systems Interface

OVERFLOW

TXCLK16I

16

16 x 5 FIFO

write

TXCLK16O

REFCLK

read

2.48832GHz

PLL

Div 16

VSC8140

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52251-0, Rev. 4.0

9/6/00

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