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VSC8140QR 查看數據表(PDF) - Vitesse Semiconductor

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VSC8140QR Datasheet PDF : 34 Pages
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Data Sheet
VSC8140
VITESSE
SEMICONDUCTOR CORPORATION
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Figure 10: Facility Loopback Data Path
RXIN+
RXIN-
RXCLKIN+
RXCLKIN-
TXOUT+
TXOUT-
TXCLKOUT+
TXCLKOUT-
FACLOOP
DQ
1
QD
0
1
0
1:16 Serial to
Parallel
16:1 Parallel to
Serial
2.48832GHz
PLL
RXOUT[15:0]
RXCLK16O
RXCLK32O
Facility Loopback
The facility loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set
high, the Facility Loopback mode is activated and the high-speed serial receive data (RXIN) is presented at the
high-speed transmit output (TXOUT), as depicted in Figure 10. In addition, the high-speed receive clock input
(RXCLKI) is selected and presented at the high-speed transmit clock output (TXCLKOUT). In Facility Loop-
back mode, the high-speed receive data (RXIN) is also converted to parallel data and presented at the low-speed
receive output pins (RXOUT[15:0]). The receive clock (RXCLKIN) is also divided down and presented at the
low-speed clock output (RXCLK16O).
Equipment Loopback Data Path
The Equipment Loopback function is controlled by the EQULOOP signal, which is active high. When the
Equipment Loopback mode is activated, the high-speed transmit data generated from the parallel to serial con-
version of the low-speed data (TXIN[15:0]) is selected and converted back to parallel data in the receiver sec-
tion and presented at the low-speed parallel data outputs (RXOUT[15:0]), as shown in Figure 11. The internally
generated OC-48 clock is used to generate the low-speed receive output clocks (RXCLK16O and
RXCLK16_32O). In Equipment Loopback mode, the transmit data (TXIN[15:0]) is serialized and presented at
the high-speed output (TXOUT) along with the high-speed transmit clock (TXCLKOUT) which is generated by
the on-chip PLL.
G52251-0, Rev. 4.0
9/6/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7

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