VSC8150QQ 查看數據表（PDF） - Vitesse Semiconductor

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VSC8150QQ

2.488Gb/s SONET/SDH Overhead Monitor

Vitesse Semiconductor 

2.488Gb/s SONET/SDH

Overhead Monitor

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8150

NOTE: References (R#-#) or (O#-#) refer to the SONET requirement or option specification listed in

Bellcore document GR-253 CORE Issue 2.

Framing

The frame acquisition algorithm determines the in-frame/out-of-frame status of the receiver. Out-of-frame

is defined as a state where the frame boundaries of the received SONET/SDH signal are unknown, i.e. after sys-

tem reset or if for some reason the receiver loses synchronization, e.g. due to ‘bit slips’. In-frame is defined as a

state where the frame boundaries are known.

Figure 1: Functional Block Diagram of Frame Acquisition Circuit

FRDETEN

SEFFRDET1

SELFRDET0

RXSIN

1:8

DMX

FRAME

DET

ERROR/ALARM

DETECTION

RXFRERR

RXSEF

RXLOF

RESYNC

FRAME SYNC.

COUNTER

BYTE

ALIGN

OUT

The receiver monitors the frame synchronization by checking for the presence of a portion of the A1/A2

framing pattern every 125uS. If one or more bit errors are detected in the expected A1/A2 framing pattern

RXFRERR will be asserted for 51.44ns. If framing pattern errors are detected for four consecutive frames a

Severely Errored Frame (SEF) alarm will be asserted (RXSEF active high) (R5-206) (See Figure 7and 10).

The frame boundary detection/verification is based on 12, 24 or 48 bits of the A1/A2 overhead (See Figure

2) depending on the setting of the SELFRDET input (See Table 1). Frame acquisition is initiated when the

FRDETEN input is held high. This control is level sensitive and the VSC8150 will continually perform frame

acquisition as long as FRDETEN is held high; a suggested implementation is to short FRDETEN logically or

physically to the SEF output. Such an arrangement will achieve realignment within 250uS or the receipt of two

error free framing patterns (R5-208).

A frame detect based on 24 bits will result in an SEF alarm at an average of no more than once every 6 min-

utes assuming a BER of 10-3 (R5-207). A frame detect based on 12 bits or 48 bits will result in a mean time

between SEF detects of 0.43 minutes and 103 minutes respectively.

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52186-0, Rev. 3.0

10/12/98

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