VSC8151 查看數據表（PDF） - Vitesse Semiconductor
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VSC8151 Datasheet PDF : 30 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
Figure 12: Serial Data Input Timing Diagram
RXSCLKIN-
RXSCLKIN+
RXSIN+
RXSIN-
TRXSCLKIN
TRXSSU TRXSH
Table 11: Serial Data Input Timing
Parameter
Description
Min
Typ
TRXSCLKIN Serial Receive clock period
401.9
—
TRXSSU
Serial Receive input data RXSIN setup time with respect
to falling edge of RXSCLKIN+
100
—
TRXSH
Serial Receive input data RXSIN hold time with respect
to falling edge of RXSCLKIN+
75
—
Figure 13: Parallel Data Input Timing Diagram
Max
—
—
—
Units
ps
ps
ps
POUTCLK
RXPIN[15:0]
TPOUTCLK
TRXPSU TRXPH
Table 12: Parallel Data Input Timing
Parameter
Description
Min
Typ
Max
Units
TPOUTCLK
TRXPSU
Parallel output clock period
Parallel receive input data RXPIN setup time with
respect to falling edge of POUTCLK output
103.2
—
6.45
ns
2.4
—
—
ns
TRXPH
Parallel receive input data RXPIN hold time with respect
to falling edge of POUTCLK output
1.0
—
—
ns
Note: Parallel output clock is synchronously generated 50/50 1/16th the frequency of the serial clock input (RXSCLKIN)
G52225-0, Rev. 2.9
12/1/99
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741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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