VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH
STS-48/STM-16 Section Terminator
Figure 16: Parallel Data Output Timing Diagram
POUTCLK
TXPOUT[15:0]
TPOUTCLK
TP
TP
Table 15: Parallel Data Output Timing
Parameter
TPOUTCLK
TP
Description
Parallel output clock period
Propagation delay from falling edge of POUTCLK to
output edge of TXPOUT[15:0]
Min
Typ
Max
Units
103.2
—
6.45
ns
-500
—
500
ps
Note: Parallel output clock is synchronously generated 50/50 1/16th the frequency of the serial clock input (RXSCLKIN)
G52225-0, Rev. 2.9
12/1/99
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741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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