VSC8163 查看數據表（PDF） - Vitesse Semiconductor
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VSC8163 Datasheet PDF : 20 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8163
OC-48 16:1 SONET/SDH
MUX with Clock Generator
Clock Generator
An on-chip PLL generates the 2.48832GHz transmit clock from the externally provided REFCLK input.
The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip
loop filter. The loop bandwidth of the PLL is within the SONET specified limit of 2MHz.
The customer can select to provide either a 77.76MHz reference (recommended), or the 2x of that refer-
ence, 155.52MHz. REF_FREQSEL is used to select the desired reference frequency. REF_FREQSEL = “0”
designates REFCLK input as 77.76MHz, REF_FREQSEL = “1” designates REFCLK input as 155.52MHz.
The REFCLK should be of high quality since noise on the REFCLK below the loop band width of the PLL
will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a
VCXO may be required to avoid passing REFCLK noise with greater than 2ps of RMS jitter to the output. The
VSC8163 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8163 itself during such
conditions.
Figure 7: AC Termination of Low-Speed LVPECL REFCLK, D[15:0] Inputs
Chip Boundary
Split-end equivalent termination is Z0 to VTERM
R1 = 83Ω R2 = 125Ω, Z0=50Ω, VTERM = VCC-2V
VCC
R1
ZO
CIN
VCC = 3.3V
R1||R2 = Zo
VCCR2 + VEER1
= VBIAS
R1+R2
R2
VEE
VCC
R1
ZO
CIN
R2
VEE
VEE = 0V
CIN typ = 100nF
for AC operation
Low-Speed Inputs
The incoming low-speed data and reference clock input are received by LVPECL inputs D[15:0] and REF-
CLK. Off-chip termination of these inputs is required. For AC-coupling, a bias voltage suitable for AC-cou-
pling needs to be provided (see Figure 7 for external biasing resistor scheme).
In most situations these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. All serial data inputs have the same circuit topology,
as shown in Figure 7. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the
G52216-0, Rev 3.3
01/05/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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