VSC8169 查看數據表（PDF） - Vitesse Semiconductor
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VSC8169 Datasheet PDF : 18 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
OC-48 (FEC) 16:1 SONET/SDH
MUX with Clock Generator
Figure 2: Enabling FIFO Operation
PLL locked to reference clock.
RESET
Minimum 5 CLK16 cycles
FIFO Mode Operation
Transparent Mode Operation
Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation.
Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.
Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/-
VSC8169
VCC
Split-end equivalent termination is ZO to VTERM
R1 = 125Ω R2 = 83Ω, Zo=50Ω, VTERM= VCC-2V
R1
R1
Zo
Zo
R1||R2 = ZO
R2
R2
VCCR2 + VEER1
R1+R2
= VTERM
VEE
Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/-
VSC8169
ZO
ZO
50Ω
50Ω
VCC-2V
G52230-0, Rev 3.6
01/02/01
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