VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8169
OC-48 (FEC) 16:1 SONET/SDH
MUX with Clock Generator
AC Characteristics
Figure 9: Parallel Input Data and Clock Timing Waveform
CLK16I+
Parallel Data Clock Input
TXIN[0:15]+, TXPRTYIN
Parallel Data Inputs
tDSU
tDH
Valid Data 1
CLK16PER
Valid Data 2
CLK16O+
Parallel Data Clock Output
= don't care
Figure 10: Serial Data and Clock Output Phase Timing Waveform
CLKOPER
DO+
Differential Serial Data Output
CLKO+
Differential Clock Output
D15
D14
MSB
tSET
D13
Time
tHOLD
D1
D0
LSB
NOTE: Bit 15 (MSB) is received first, Bit 0 (LSB) is received last.
G52230-0, Rev 3.6
01/02/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 7