VSC8169QR 查看數據表（PDF） - Vitesse Semiconductor
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VSC8169QR Datasheet PDF : 18 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
OC-48 (FEC) 16:1 SONET/SDH
MUX with Clock Generator
Preliminary Data Sheet
VSC8169
Table 1: AC Characteristics
Parameters
tDSU
tDH
Description
Data setup time to the rising
edge of CLK16I+
Data hold time after the rising
edge of CLK16+
tDOR,tDOF
tCLKR, tCLKF
CLK16OD
CLKID
RCKD
CLKOD
CLKOPER
DO± rise and fall time
CLK16O± rise and fall times
CLK16O± duty cycle
CLK16I± duty cycle
Reference Clock duty cycle
CLKO duty cycle
CLKO period
CLK16OPER
tSET
tHOLD
CLK16O period
DO setup time with respect to
rising CLKO edge
DO hold time with respect to
rising CLKO edge
Min Typ Max Units
0.75 —
—
ns
Conditions
1.0
—
—
—
— 120
—
— 250
40
—
60
30
—
70
40
—
60
40
—
60
— 401.9 —
—
6.4
—
—
90
—
—
310
—
ns
ps
20% to 80% into 100Ω load
See Figure 6
ps See Figures 3 and 4
%
% Assuming 10% distortion of CLKO
%
%
ps
SONET-based 77.76MHz or
155.52MHz reference clock
ns
SONET-based 77.76MHz or
155.52MHz reference clock
ps
Inverting CLKO will switch
(approx) tSET and tHOLD values.
ps
Inverting CLKO will switch
(approx) tset and thold values.
Clock Multiplier Performance
TDJ
Output data jitter
TCJ
Jittertol
Output clock jitter
Jitter tolerance
Tuning Range
rms, tested to SONET specification
—
—
4
ps (12kHz to 20MHz) with 2ps rms
jitter on REFCLK.
rms, tested to SONET specification
—
—
4
ps (12kHz to 20MHz) with 2ps rms
jitter on REFCLK.
—
—
—
— Exceeds SONET/SDH mask
-100
+100 ppm
Figure 11: Differential and Single-Ended Input/Output Voltage Measurement
b
= α Single
Ended
a
Swing
b
Differential
Swing = α
a
* Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single-ended swing.
Differential swing is specified as equal in magnitude to single-ended swing.
Page 8
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52230-0, Rev 3.6
01/02/01
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