W78E51C 查看數據表（PDF） - Winbond

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W78E51C

8-BIT MICROCONTROLLER

Winbond 

W78E51C

6.6 Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to

deglitch the reset line when the W78E51C is used with an external RC network. The reset logic also

has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit

4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

7. SECURITY BITS

During the programmer operation mode, the Flash EPROM can be programmed and verified

repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The

protection of Flash EPROM and those operations on it are described below. The W78E51C has a

Special Setting Register, the Security Register, which can be accessed in normal mode. The register

can only be accessed from the Flash EPROM operation mode. Those bits of the Security Registers

can not be changed once they have been programmed from high to low. They can only be reset

through erase-all operation. The Security Register is addressed in the Flash EPROM operation mode

by address #0FFFFh.

D7 D6 D5 D4 D3 D2 D1 D0

B7 Reserved B2 B1 B0

Security Bits

4KB Flash EPROM 0000h

Program Memory

B0 : Lock bit, logic 0 : active

B1 : MOVC inhibit,

logic 0 : the MOVC instruction in external memory

cannot access the code in internal memory.

logic 1 : no restriction.

B2 : Encryption

logic 0 : the encryption logic enable

logic 1 : the encryption logic disable

Reserved

0FFFh

B7 : Osillator Control

logic 0 : 1/2 gain

logic 1 : Full gain

Default 1 for all security bits. Reserved bits must be kept in logic 1.

Security Register 0FFFFh

Special Setting Register

7.1 Lock Bit

This bit is used to protect the customer's program code in the W78E51C. It may be set after the

programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the

on-chip ROM data and Special Setting Registers can not be accessed again.

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Publication Release Date: April 20, 2005

Revision A2

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