W986416DH 查看數據表（PDF） - Winbond

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W986416DH

1M x 4 BANKS x 16 BITS SDRAM

Winbond 

W986416DH

Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled

burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto-precharge cannot be interrupted before the entire burst operation

is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is prohibited

during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank

cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge

command is illegal if the burst is set to full page length. If A10 is high when a Write Command is

issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the

precharge operation one clock delay from the last burst write cycle. This delay is referred to as write

tDPL. The bank undergoing auto-precharge cannot be reactivated until tWR and tRP are satisfied. This is

referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command,

the interval between the Bank Activate Command and the beginning of the internal precharge

operation must satisfy tRAS (min).

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The

Precharge Command is entered when CS , RAS and WE are low and CAS is high at the

rising edge of the clock. The Precharge Command can be used to precharge each bank separately or

all banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is

to be precharged when the command is issued. After the Precharge Command is issued, the

precharged bank must be reactivated before a new read or write access can be executed. The delay

between the Precharge Command and the Activate Command must be greater than or equal to the

Precharge time (tRP).

Self Refresh Command

The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE

high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.

Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.

When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are

disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will

exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the

device exits Self Refresh Operation and before the next command can be issued. This delay is equal

to the tAC cycle time plus the Self Refresh exit time.

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly

distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and

just after exiting the self refresh mode.

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are

gated off to reduce the power. The Power Down mode does not perform any refresh operations,

therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the

device.

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation

Command is required on the next rising clock edge, depending on tCK. The input buffers need to be

enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.).

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