W9425G6EH 查看數據表（PDF） - Winbond

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W9425G6EH

4 M × 4 BANKS × 16 BITS DDR SDRAM

Winbond 

6. BLOCK DIAGRAM

W9425G6EH

CLK

CLK

CKE

DLL

CLOCK

BUFFER

CS

RAS

CAS

WE

COMMAND

DECODER

CONTROL

SIGNAL

GENERATOR

A10

A0

A9

A11

A12

BA0

BA1

ADDRESS

BUFFER

MODE

REGISTER

REFRESH

COUNTER

COLUMN

COUNTER

COLUMN DECODER

CELL ARRAY

BANK #0

SENSE AMPLIFIER

PREFETCH REGISTER

DATA CONTROL

CIRCUIT

COLUMN DECODER

CELL ARRAY

BANK #2

SENSE AMPLIFIER

COLUMN DECODER

CELL ARRAY

BANK #1

SENSE AMPLIFIER

DQ

BUFFER

COLUMN DECODER

CELL ARRAY

BANK #3

SENSE AMPLIFIER

NOTE: The cell array configuration is 8192 * 512 * 16

DQ0

DQ15

LDQS

UDQS

LDM

UDM

Publication Release Date:Dec. 03, 2008

-8-

Revision A08

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