STFLSTUDIO2/KIT 查看數據表（PDF） - STMicroelectronics

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STFLSTUDIO2/KIT

8-BIT FUZZY CO-PROCESSOR

STMicroelectronics 

W.A.R.P.2.0

PIN DESCRIPTION

Signals READY, RD, WAIT, DS, BUSY, LASTIN

and O11 ( external A/D Start Conversion) have

programmable polarity, see table 6 for default

values.

VDD, VSS. Power is supplied to W.A.R.P. using

these pins. VDD is the power connection and VSS is

the ground connection; multi-connections are nec-

essary.

MCLK. Master Clock (Input): This is the input

master clock whose frequency can reach up to

40MHz (MAX).

During the Off-Line phase with AUTO High, the

MCLK is internally divided to utilize boot memories

working with a slower frequency.The access speed

is presettable by means of SIS0-SIS2 pins.

PRESET. Preset (Input, active Low) : This is the

restart pin of W.A.R.P.. It is possible to restart the

work during the computation (On-Line phase) or

before the writing of internal memories (Off-Line

phase). In both cases it must be put Low at least

for a clock period. After PRESET Low the proces-

sor remains in the reset status 3 MCLK pulses.

AUTO. Auto-Boot: (Input, active High): During the

Off-Line phase AUTO High enables the automatic

boot of W.A.R.P.2.0 whereas AUTO Low validates

the manual downloading. The manual boot has to

be performed using the handshaking signals

RD/READY.

During the On-Line phase AUTO High disables

the generation of the Start A/D conversion (O11)

signal.

SIS0-SIS2. Speed & Input Selection (Inputs): Dur-

ing the Off-Line phase with AUTO High (Auto-Boot)

SIS bus allows to choose the speed of downloading

from the external memory which contains the start-

up configuration of W.A.R.P.2.0. In that case (Auto-

Boot) MCLK is internally divided to provide a slower

sinchronization signal which is automatically used

as RD for the reading of the external memory. Table

2 shows how to preset the frequency of this syn-

chronization signal.

During the On-Line phase in Slave mode (see

Register Bench description, Tab.5) SIS bus allows

to provide W.A.R.P.2.0 with inputs in any order by

specifying their identification number. The input

and its identification number (SIS0-SIS2) will be

acquired at the next active RD so they must be

already stable when RD is given.

Table 2. Downloading Speed

SIS0

Low

High

SIS1

Low

Low

SIS2

Low

Low

Internal Synchronization

Signal Frequency

MCLK/32

MCLK/16

I0-I7. Input bus (Input): During the Off-Line phase

these 8 data input pins accept addresses and data

from the external boot memory containing

W.A.R.P.2.0 configuration. This start-up memory

(which can be a ZERO-POWER, the host proces-

sor memory, an EPROM, a Flash, the PC Memory,

etc.) contains the fuzzy project built by means of

FUZZYSTUDIO™ 2.0.

In On-Linemode this bus carries the input variables

according to the prefixed order.

OFL. Offline (Input, active High): When this pin is

High, the chip is enabled to load data in the internal

RAMs (Off-Line phase). It must be Low when the

fuzzy controller is waiting for input values and

during the processing phase (On-Line phase).

When OFL changes its status the processor re-

mains presetted for 3 clock pulses.

LASTIN. Last Input (Input, default active High):

During the On-Line phase in slave mode (see

Register Bench description, table 5) LASTIN High

indicates no other inputs have to be provided so

W.A.R.P.2.0 can start the processing phase.

W.A.R.P.2.0 inputs are those in the input interface

so if some variables do not need to be acquired

again (because they change slower than others)

they remain stored and no extra time is required to

acquire them again.

OE. Output Enable (Input, active Low): OE Low

enables O0-011output bus or (if High) put it in

3-STATE.

WAIT. Wait (Input, default active High): This pin

High stops the output processing. When WAIT is

enabled W.A.R.P.2.0 finishes to compute the cur-

rent output variable but it does not give it on the

output bus until WAIT becomes Low. This signal

allows to synchronize W.A.R.P.2.0 with slower de-

vices.

RD. Read (Input, default active High): Both in

Off-Line and in On-Line mode RD indicates data

are ready to be acquired from the input bus I0-I7.

READY. Ready (Output, default active High): Both

in Off-Line and in On-Line mode RD indicates data

have been acquired from the input bus I0-I7 and

are now stored in W.A.R.P.2.0 internal registers.

ENDOFL. End of Off-Line phase (Output, active

High): This pin indicates the end of the download-

ing phase (Off-Line) so the content of the boot

memory is already stored in W.A.R.P.2.0 internal

memories. After ENDOFL is active the user can put

OFL Low so the On-Line phase can start.

BUSY. Busy Signal (Output, default active High):

When the elaboration phase is running this pin is

active. When W.A.R.P.2.0 finishes to compute the

last output variable, it puts BUSY Low and waits

for new inputs.

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