WEDPNF8M721V-1012BM 查看數據表（PDF） - Unspecified

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WEDPNF8M721V-1012BM

8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package

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FIG. 4 CAS LATENCY

WEDPNF8M721V-XBX

n+m. The I/Os will start driving as a result of the clock edge

one cycle earlier (n + m - 1), and provided that the rel-

evant access times are met, the data will be valid by clock

edge n + m. For example, assuming that the clock cycle

time is such that all relevant access times are met, if a READ

command is registered at T0 and the latency is programmed

to two clocks, the I/Os will start driving after T1 and the

data will be valid by T2. Table 2 indicates the operating fre-

quencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by setting M7and

M8 to zero; the other combinations of values for M7 and M8

are reserved for future use and/or test modes. The pro-

grammed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used be-

cause unknown operation or incompatibility with future

versions may result.

WRITE BURST MODE

When M9 = 0, the burst length programmed via M0-M2

applies to both READ and WRITE bursts; when M9 = 1, the

programmed burst length applies to READ bursts, but write

accesses are single-location (nonburst) accesses.

COMMANDS

The Truth Table provides a quick reference of available com-

mands. This is followed by a written description of each

command. Three additional Truth Tables appear following

the Operation section; these tables provide current state/

next state information.

TABLE 2 - CAS LATENCY

SPEED

-100

-125

ALLOWABLE OPERATING

FREQUENCY (MHZ)

CAS

LATENCY = 2

CAS

LATENCY = 3

£ 75

£ 100

£ 100

£ 125

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands

from being executed by the SDRAM, regardless of whether

the CLK signal is enabled. The SDRAM is effectively dese-

lected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a

NOP to an SDRAM which is selected (CS is LOW). This pre-

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