WM8195(2002) 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8195 Datasheet PDF : 31 Pages
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WM8195
PIN CONFIGURATION
VRX
VRLC/VBIAS
AGND1
BINP
AGND2
GINP
AGND3
RINP
AGND4
DVDD1
OEB
SEN/STB
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
DGND4
DVDD3
OP[10]
OP[9]
OP[8]
OP[7]
DGND3
OP[6]
OP[5]
OP[4]
OP[3]
DGND2
Advanced Information
ORDERING INFORMATION
DEVICE
XWM8195CFT
TEMP. RANGE
0 to 70°C
PACKAGE
48-pin TQFP
1mm thick body
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
VRX
Analogue output Input return bias voltage.
This pin must be decoupled to AGND via a capacitor.
2 VRLC/VBIAS Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be decoupled to AGND via a capacitor.
VRLC can be externally driven if programmed Hi-Z.
3
AGND1
Supply
Analogue ground (0V).
4
BINP
Analogue input Blue channel input video.
5
AGND2
Supply
Analogue ground (0V).
6
GINP
Analogue input Green channel input video.
7
AGND3
Supply
Analogue ground (0V).
8
RINP
Analogue input Red channel input video.
9
AGND4
Supply
Analogue ground (0V).
10
DVDD1
Supply
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
11
OEB
Digital input Output Hi-Z control, all digital outputs disabled when OEB = 1.
12
SEN/STB
Digital input Serial interface: enable pulse, active high Parallel interface: strobe, active low
Latched on NRESET rising edge: if Low then device control is via serial interface,
if high then device control is via parallel interface.
13
SDI/DNA
Digital input Serial interface: serial input data signal
Parallel interface:
High = data, Low = address
14
SCK/RNW
Digital input Serial interface: serial clock signal
Parallel interface:
High: OP[13:6] is output bus.
Low: OP[13:6] is input bus (Hi-Z).
15
VSMP
Digital input Video sample synchronisation pulse.
16
RLC/ACYC
Digital input RLC (active high) selects reset level
ACYC autocycles between R, G, B
clamp on a pixel-by-pixel basis – tie high inputs when in Line-by-Line mode.
if used on every pixel.
17
MCLK
Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
18
DGND1
Supply
Digital ground (0V).
19
NC
No connection.
20
NC
No connection.
w
AI Rev 2.0 September 2002
2
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