WM8195(2002) 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8195 Datasheet PDF : 31 Pages
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Advanced Information
INPUT VIDEO SAMPLING
MCLK
VSMP
INPUT
VIDEO
tPER
tMCLKH tMCLKL
tVSMPSU
tVSMPH
tVSU
tVH
WM8195
tRSU tRH
Figure 1 Input Video Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
MCLK period
SYMBOL
tPER
TEST CONDITIONS
MIN
41.6
MCLK high period
tMCLKH
18.8
MCLK low period
tMCLKL
18.8
VSMP set-up time
tVSMPSU
6
VSMP hold time
tVSMPH
3
Video level set-up time
tVSU
10
Video level hold time
tVH
3
Reset level set-up time
tRSU
10
Reset level hold time
tRH
3
Notes:
1. tVSU and tRSU denote the set-up time required after the input video signal has settled.
2. Parameters are measured at 50% of the rising/falling edge.
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUTPUT DATA TIMING
MCLK
tPD
OP[13:0]
Figure 2 Output Data Timing
w
AI Rev 2.0 September 2002
7
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