Advanced Information
WM8195
SERIAL INTERFACE
SCK
SDI
SEN
SDO
tSPER
tSSU
tSH
tSCKL tSCKH
tSCE
ADC DATA
tSEW tSEC
tSERD
tSCRD
t
SCRDZ
MSB
LSB
REGISTER DATA
ADC
DATA
Figure 5 Serial Interface Timing
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz
unless otherwise stated.
PARAMETER
SCK period
SYMBOL
tSPER
TEST CONDITIONS
SCK high
tSCKH
SCK low
tSCKL
SDI set-up time
tSSU
SDI hold time
tSH
SCK to SEN set-up time
tSCE
SEN to SCK set-up time
tSEC
SEN pulse width
tSEW
SEN low to SDO = Register data
tSERD
SCK low to SDO = Register data
tSCRD
SCK low to SDO = ADC data
tSCADC
Note: Parameters are measured at 50% of the rising/falling edge.
MIN
41.6
18.8
18.8
6
6
12
12
25
TYP
MAX
30
30
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
w
AI Rev 2.0 September 2002
9