WM8195 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8195 Datasheet PDF : 33 Pages
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Production Data
WM8195
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz unless
otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
Overall System Specification (including 14-bit ADC, PGA, Offset and CDS functions)
NO MISSING CODES GUARANTEED
Conversion rate
12
Full-scale input voltage range
(see Note 1)
Max Gain
0.4
Min Gain
4.08
Input signal limits (see Note 2)
VIN
0
Full-scale transition error
Gain = 0dB;
20
PGA[7:0] = 4B(hex)
Zero-scale transition error
Gain = 0dB;
20
PGA[7:0] = 4B(hex)
Differential non-linearity
DNL
1.25
Integral non-linearity
INL
8
Channel to channel gain matching
1
Total output noise
Min Gain
1
Max Gain
3
References
Upper reference voltage
VRT
2.85
Lower reference voltage
VRB
1.35
Input return bias voltage
VRX
1.65
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRTB
1.4
1.5
1
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
50
VRLC short-circuit current
5
VRLC output resistance
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
RLCDAC resolution
4
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCSTEP
VRLCSTEP
VRLCBOT
0.25
0.17
0.39
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
0.26
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
4.16
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
2.81
VRLC deviation
-50
Offset DAC, Monotonicity Guaranteed
Resolution
8
Differential non-linearity
DNL
0.1
Integral non-linearity
INL
0.25
Step size
2.04
Output voltage
Code 00(hex)
-260
Code FF(hex)
+260
Notes:
1. Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.
2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
MAX
UNIT
AVDD
MSPS
Vp-p
Vp-p
V
mV
mV
LSB
LSB
%
LSB rms
LSB rms
V
V
V
1.6
V
Ω
Ω
mA
Ω
1
µA
bits
V/step
V/step
V
V
V
V
+50
mV
bits
0.5
LSB
1
LSB
mV/step
mV
mV
w
PD Rev 4.1 July 2005
7
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