WM8198 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8198 Datasheet PDF : 31 Pages
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WM8198
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND = DGND = 0V, TA = 25°C, MCLK = 12MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Conversion Rate
HIGHSPEED = 0,
6
HIGHSPEED = 1, MCLK = 24MHz
12
Full-scale input voltage range,
PGAMODE=0. (see Note 1)
Max Gain
0.4
Min Gain
4.08
Full-scale input voltage range,
PGAMODE=1. (see Note 1)
Max Gain
0.6
Min Gain
3
Input signal limits (see Note 2)
VIN
0
Full-scale transition error
Gain = 0dB;
20
PGA[8:0] = 96(hex)
Zero-scale transition error
Gain = 0dB;
20
PGA[8:0] = 96(hex)
Differential non-linearity
DNL
1.25
Integral non-linearity
INL
20
Total output noise
Min Gain
3.9
Max Gain
11
Channel to channel gain matching
1
References
Upper reference voltage
VRT
2.85
Lower reference voltage
VRB
1.35
Input return bias voltage
VRX
1.65
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRTB
1.4
1.5
1
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
50
VRLC short-circuit current
2
VRLC output resistance
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
RLCDAC resolution
4
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCSTEP
VRLCSTEP
VRLCBOT
AVDD = 5.0V
AVDD = 5.0V
0.25
0.17
0.39
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
0.26
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
AVDD = 5.0V
4.14
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
2.81
VRLC deviation
25
Offset DAC, Monotonicity Guaranteed
Resolution
8
Differential non-linearity
DNL
0.1
Integral non-linearity
INL
0.25
Step size
2.04
Output voltage
Code 00(hex)
-260
Code FF(hex)
+260
Notes:
1.
Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
MAX
AVDD
1.6
1
0.5
1
UNIT
MSPS
MSPS
Vp-p
Vp-p
Vp-p
Vp-p
V
mV
mV
LSB
LSB
LSB rms
LSB rms
%
V
V
V
V
Ω
Ω
mA
Ω
µA
bits
V/step
V/step
V
V
V
V
mV
bits
LSB
LSB
mV/step
mV
mV
w
PD Rev 4.0 June 2004
6
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