WM8198 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8198 Datasheet PDF : 31 Pages
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WM8198
INPUT VIDEO SAMPLING
tPER
tMCLKH tMCLKL
MCLK
VSMP
INPUT
tVSMPSU
tVSMPH
tVSU
tVH
VIDEO
Production Data
tRSU
tRH
Figure 1 Input Video Timing
Note:
1.
See Page 14 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND = DGND = 0V, TA = 25°C unless otherwise stated.
PARAMETER
MCLK period
SYMBOL
tPER
TEST CONDITIONS
MIN
83.3
MCLK high period
tMCLKH
37.5
MCLK low period
tMCLKL
37.5
VSMP set-up time
tVSMPSU
10
VSMP hold time
tVSMPH
5
Video level set-up time
tVSU
15
Video level hold time
tVH
5
Reset level set-up time
tRSU
15
Reset level hold time
tRH
5
Notes:
1.
tVSU and tRSU denote the set-up time required after the input video signal has settled.
2.
Parameters are measured at 50% of the rising/falling edge.
TYP
OUTPUT DATA TIMING
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK
tPD
OP[7:0]
Figure 2 Output Data Timing
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PD Rev 4.0 June 2004
9
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