WM8860 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8860 Datasheet PDF : 184 Pages
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Pre-Production
PIN DESCRIPTION
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NAME
VIN1LP
VIN1LN
VIN1RP
VIN1RN
VIN2LP
VIN2LN
VIN2RP
VIN2RN
MICBIAS
GPIO1
GPIO2
DGND
/RESET
SYNC
SDO
BCLK
SDI
SPDIFOUT
DBVDD
DGND
DCVDD
DMICCLK
DMICDAT1
DMICDAT2
DNC
DNC
DNC
DNC
VOUT2RN
VOUT2RP
VOUT2LN
VOUT2LP
VOUT1R
VOUT1L
HPVSS
HPVDD
CFB2
HPGND
CFB1
CPCAP
CPVDD
AGND
AVDD
VREFP
VMID
VREFN
JACKDET1
JACKDET2
TYPE
Analogue input
Analogue input
Analogue input
Analogue input
Analogue input
Analogue input
Analogue input
Analogue input
Analogue output
Digital input / output
Digital input / output
Supply input
Digital input
Digital input
Digital input
Digital input
Digital input / output
Digital output
Supply input
Supply input
Supply input
Digital output
Digital input
Digital input / output
Analogue output
Analogue output
Analogue output
Analogue output
Analogue output
Analogue output
Supply output
Supply output
Analogue output
Supply input
Analogue output
Supply output
Supply input
Supply input
Supply input
Analogue output
Analogue output
Analogue output
Analogue output
Analogue output
WM8860
DESCRIPTION
Left channel 1 positive input
Left channel 1 negative input
Right channel 1 positive input
Right channel 1 negative input
Left channel 2 positive input
Left channel 2 negative input
Right channel 2 positive input
Right channel 2 negative input
Microphone bias output
General purpose digital input/output 1
General purpose digital input/output 2
Digital ground (return for DBVDD and DCVDD)
Global reset (active low)
HDA frame sync, 48kHz
Serial data output from HDA controller
HDA Link bit clock, 24MHz
Serial data input to HDA controller
S/PDIF output
Digital buffer supply input
Digital ground (return for DBVDD and DCVDD)
Digital core supply input
Digital microphone clock output
Digital microphone data input 1
Digital microphone data input 2
Reserved - Do not connect
Reserved - Do not connect
Reserved - Do not connect
Reserved - Do not connect
Right channel 2 negative output
Right channel 2 positive output
Left channel 2 negative output
Left channel 2 positive output
Right channel 1 output
Left channel 1 output
Charge pump negative supply decoupling point
Charge pump positive supply decoupling point
Charge pump flyback capacitor pin 2
Charge pump ground (return path for HPVDD and HPVSS)
Charge pump flyback capacitor pin 1
Internally generated regulated charge pump supply decoupling point
Charge pump supply input
Analogue ground (return path for AVDD and CPVDD)
Analogue supply input
Analogue positive reference decoupling point
Midrail voltage decoupling point
Analogue negative reference decoupling point
Jack detect sense 1
Jack detect sense 2
w
PP, April 2011, Rev 3.2
9
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