WM8912
Production Data
SIGNAL TIMING REQUIREMENTS
COMMON TEST CONDITIONS
Unless otherwise stated, the following test conditions apply throughout the following sections:
• Ambient temperature = +25°C
• DCVDD = 1.0V
• DBVDD = AVDD = CPVDD = 1.8V
• DGND = AGND = CPGND = 0V
Additional, specific test conditions are given within the relevant sections below.
MASTER CLOCK
MCLK
Figure 1 Master Clock Timing
tMCLKY
tMCLKL tMCLKH
Master Clock Timing
PARAMETER
MCLK cycle time
MCLK duty cycle
SYMBOL
TMCLKY
TMCLKDS
TEST CONDITIONS
MCLK_DIV=1
MCLK_DIV=0
MIN
40
80
60:40
TYP
MAX
40:60
UNIT
ns
ns
w
PD, Rev 4.0, September 2010
14