WM8912 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8912
Wolfson Microelectronics plc
WM8912 Datasheet PDF : 128 Pages
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Production Data
CONTROL INTERFACE TIMING
WM8912
Figure 4 Control Interface Timing
Test Conditions
DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK =
256fs, 24-bit data, unless otherwise stated.
PARAMETER
SCLK Frequency
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
SDA, SCLK Rise Time
SDA, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
Pulse width of spikes that will be suppressed
SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
MIN
1300
600
600
600
100
600
0
TYP
MAX
400
300
300
900
5
UNIT
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
w
PD, Rev 4.0, September 2010
17
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