X24C16 查看數據表（PDF） - Xicor -> Intersil

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X24C16

2048 x 8 Bit 16K Serial E2PROM

Xicor -> Intersil 

X24C16

DEVICE OPERATION

The X24C16 supports a bidirectional bus oriented pro-

tocol. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is a

master and the device being controlled is the slave. The

master will always initiate data transfers, and provide

the clock for both transmit and receive operations.

Therefore, the X24C16 will be considered a slave in all

applications.

Figure 1. Data Validity

Clock and Data Conventions

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are re-

served for indicating start and stop conditions. Refer to

Figures 1 and 2.

Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL is

HIGH. The X24C16 continuously monitors the SDA and

SCL lines for the start condition and will not respond to

any command until this condition has been met.

SCL

SDA

DATA STABLE DATA

CHANGE

3840 FHD F06

3

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