X24C04PMG 查看數據表（PDF） - IC MICROSYSTEMS

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X24C04PMG

Serial E²PROM

IC MICROSYSTEMS 

X24C04

Sequential Read

Sequential Read can be initiated as either a current

address read or random access read. The first word is

transmitted as with the other modes, however, the

master now responds with an acknowledge, indicating it

requires additional data. The X24C04 continues to out- put

data for each acknowledge received. The read

operation is terminated by the master; by not responding with

an acknowledge and by issuing a stop condition.

Figure 9. Sequential Read

The data output is sequential, with the data from address n

followed by the data from n + 1. The address counter

for read operations increments all address bits, allowing the

entire memory contents to be serially read during

one operation. At the end of the address space (address 511),

the counter “rolls over” to address 0 and the

X24C04 continues to output data for each acknowledge

received. Refer to Figure 9 for the address, acknowledge

and data transfer sequence.

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

SDA LINE

A

BUS ACTIVITY:

C

X24C04

K

DATA n

A

A

A

C

C

C

K

K

K

DATA n+1

DATA n+2

S

T

O

P

P

DATA n+x

3839 FHD F16

Figure 10. Typical System Configuration

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

V

CC

PULL-UP

RESISTORS

3839 FHD F17

8

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