X5043 查看數據表（PDF） - Intersil

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产品描述 (功能)

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X5043

CPU Supervisor with 4K SPI EEPROM

Intersil 

X5043, X5045

WP

CS

SCK

SI

VP = 15-18V

0 1 23 4 56 7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

8 Bits

06h

WREN

02h

Write

03h

Address

FIGURE 2. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15–18V)

00h

Data

VTRIP

Adj.

VP

Adjust

Run

1

8

2 X5043 7

3 X5045 6

4

5

4.7K

RESET

FIGURE 3. SAMPLE VTRIP RESET CIRCUIT

µC

SCK

SI

SO

CS

7

FN8126.1

September 16, 2005

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