AD6630 查看數據表（PDF） - Analog Devices

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AD6630

Differential, Low Noise IF Gain Block with Output Clamping

Analog Devices 

AD6630

J6 1

SMA

2

J7 1

SMA

2

AGND

AGND

T1

61

2

43

L1

470nH

C12

10nF

C11

10nF

TC4 –1W

AT224

C1

10nF

AGND

AGND

C17

10nF

C18

1␮F

+–

C21

10nF

AD6630

1

U1

16

NC1

VCC1

2

15

NC2

CD1

3

IP2

14

OP

4

IP1

5

IP1B

13

VEE

12

CMD

6

IP2B

11

OPB

7

CL1

10

CD2

8

CL2

9

VCC2

J2

C20

1nF

J1

PCTB3

3 21

AGND

J3

11

2

C13

1␮F

12

+–

C16

10nF

AGND

AGND

R3

AGND

C15 C10

1nF

100nF

C5 10nF

R1

200⍀

TP1

1

TEST P

C2

10nF

C6 10nF

T2

34

2

C8

C9 L2

C7 10nF

C14

1nF

C19

100nF

C4

100nF

AGND

C3

10nF

AGND

R2

200⍀

16

TC 8-1

AT224

TP2

1

TEST P

AGND

Figure 14. Evaluation Board Schematic

1 J8

SMA

2

AGND

Frequency

(MHz)

70

170

200

250

Table I. Typical S Parameters

S11

224.5 ∠ –4.52°

264.8 ∠ –32.9°

227.9 ∠ –34.8°

209.5 ∠ –36.2°

S12

–41.0 ∠ –3.0°

–31.4 ∠ 0°

–41.0 ∠ –5°

–40.6 ∠ –2.3°

S21

24.1 ∠ –8.8°

23.5 ∠ –22.5°

23.2 ∠ –26.4°

22.9 ∠ –38.9°

S22

394.3 ∠ –8.6°

382.4 ∠ –21.9°

353.0 ∠ –25.4°

328.9 ∠ –29.2°

REV. 0

–7–

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