CMX980A 查看數據表（PDF） - MX-COM Inc

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CMX980A

Digital Radio Baseband Processor

MX-COM Inc  

Digital Radio Baseband Processor

12

CMX980A Advance Information

4.4.3 Offset Registers

System generated offsets may be removed by control of the offset register via the serial interface.

4.4.4 I and Q Channel Gain

Programmable gain modules are provided in both I and Q channels. These blocks allow the user to adjust

the dynamic range of the received data within the digital filters, thus optimizing the filter signal to noise

performance for a range of levels at the Rx input pins. In the receive section the gain-multiplier sign bit is user

accessible, therefore phase inversion in each channel is possible by programming negative numbers into the

gain registers.

The two channels are independently programmable. This enables differential gain corrections to be made

within the digital domain.

4.5 Auxiliary Circuits

4.5.1 10-Bit DACs

Four 10-bit DACs are provided to assist in a variety of control functions. The DACs are designed to provide

an output as a proportion of the supply voltage, depending on the digital input. They are monotonic with an

absolute accuracy of better than 1%. Control and Data for these come via the serial interface.

4.5.2 10-Bit ADC

A 10-bit ADC is provided to assist in a variety of measurement and control functions. The ADC is designed to

produce a digital output proportional to the input voltage; full scale being the positive supply. It is monotonic

with an absolute accuracy of about 1%. An input multiplexer allows the input to be selected from one of four

sources. Control and digital data output is via the serial interface.

4.5.3 Power Ramping and Control

One of the DACs has an additional feature that enables a set of values to be sequenced out at a pre-selected

frequency. This is aimed at enabling power ramping of a RF output with a suitable profile. The sequence may

be reversed for power down. The sequence of values is stored in a dedicated RAM, which can be loaded via

the serial interface.

4.6 IRQ Function

An interrupt request (IRQ) pin (labeled N_IRQ) is provided for asynchronous communication with an external

processor. The N_IRQ pin will be asserted (taken low) when any of the error or user information flags are

activated by an internal operation. Some examples of operations that may generate an interrupt are:

1. An attempt by the user to write to a full Tx data-input FIFO

2. An attempt is made by the Tx to read from the Tx data-input FIFO when it is empty.

3. An internal arithmetic overflow has occurred in an FIR filter.

The IRQ feature may also be used to establish the phasing of the received I and Q channel data from the

RxDat serial port should synchronization be lost for any reason.

The cause of the IRQ can be obtained by reading the error flags register. All possible causes of an IRQ are

masked on reset. Mask status can be altered by writing to the IRQ mask register.

Note that default coefficients and settings have been optimized to maximize performance and should not

cause arithmetic overflows. However, use of non-default coefficients, large offset corrections or large Tx

phase adjustments may cause problems, which can be corrected by scaling down coefficients or via the gain

multiplier feature.

Additionally, the internal symbol-clock signal may be brought out to this pin. This is intended for a number of

uses, primarily in the following areas:

1. In multi-chip systems where symbol phase synchronization between devices is necessary.

2. To assist in timing the write operations to the 79-tap filter input in direct write mode.

3. To provide a reference signal during phase synchronization to the BS symbol clock.

2000 MX-COM, Inc.

www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054

Doc. 20480201.001

4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA

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