AD9501JN(RevB) 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD9501JN Datasheet PDF : 12 Pages
| |||
AD9501–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+VS = 5 V; CEXT = Open; RSET = 3090 ⍀ [Full-Scale Range = 100 ns]; Pin 8 grounded
and device output connected to Pin 4 RESET input, unless otherwise noted.)
Parameter
0؇C to 70؇C
Test
AD9501JN/JP
Temp Level Min
Typ
Max
Unit
RESOLUTION
8
Bits
ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Monotonicity
25∞C I
25∞C I
25∞C I
0.5
LSB
1
LSB
Guaranteed
DIGITAL INPUTS
Latch Input 1 Voltage
Full
VI
2.0
V
OBSOLETE Latch Input 0 Voltage
Full
VI
0.8
V
Logic 1 Voltage
Full
VI
2.0
V
Logic 0 Voltage
Full
VI
0.8
V
Logic 1 Current
Logic 0 Current
Digital Input Capacitance
Data Setup Time (tS)1
Data Hold Time (tH)2
Latch Pulse Width (tL)
Reset/Trigger Pulse Width (tR, tT)
Full
VI
Full
VI
25∞C IV
25∞C V
25∞C V
25∞C V
25∞C V
60
mA
3
mA
5.5
pF
2.5
ns
2.5
ns
3.5
ns
2
ns
DYNAMIC PERFORMANCE
Maximum Trigger Rate3
25∞C IV
18
22
MHz
Minimum Propagation Delay (tPD)4 25∞C I
25
30
ns
Propagation Delay Tempco5
Full
V
25
ps/∞C
Full-Scale Range Tempco
Full
V
36
ps/∞C
Delay Uncertainty
25∞C V
53
ps
Reset Propagation Delay (tRD)6
25∞C I
14.5
17.5
ns
Reset-to-Trigger Holdoff (tTHO)7
25∞C V
4.5
ns
Trigger-to-Reset Holdoff (tRHO)8
25∞C V
19
ns
Minimum Output Pulse Width9
25∞C V
7.5
ns
Output Rise Time10
25∞C I
2.3
3.5
ns
Output Fall Time10
25∞C I
1.0
2.0
ns
DAC Settling Time (tLD)11
25∞C V
30
ns
Linear Ramp Settling Time (tLRS)12
25∞C
V
20
ns
DIGITAL OUTPUT
Logic 1 Voltage (Source 1 mA)
Full
VI
2.4
V
Logic 0 Voltage (Sink 4 mA)
Full
VI
0.24
0.4
V
POWER SUPPLY13
Positive Supply Current (5.0 V)
Full
VI
Power Dissipation
Full
VI
Power Supply Rejection Ratio14
Full-Scale Range Sensitivity
25∞C I
Minimum Prop Delay Sensitivity 25∞C I
69.5
83
mA
415
mW
0.7
2.0
ns/V
0.45
1.7
ns/V
NOTES
11Digital data inputs must remain stable for the specified time prior to the positive transition of the LATCH signal.
12Digital data inputs must remain stable for the specified time after the positive transition of the LATCH signal.
13Programmed delay (tD) = 0 ns. Maximum self-resetting trigger rate is limited to 6.9 MHz with 100 ns programmed delay. If tD = 0 ns and external RESET signal is
used, maximum trigger rate is 23 MHz.
14Programmed delay (tD) = 0 ns. In operation, any programmed delays are in addition to the minimum propagation delay (tPD).
15Programmed delay (tD) = 0 ns. Minimum propagation delay (tPD).
16Measured from 50% transition point of the RESET signal input to the 50% transition point of the falling edge of the output.
17Minimum time from the falling edge of RESET to the triggering input to ensure valid output pulse, using external RESET pulse.
18Minimum time from triggering event to rising edge of RESET to ensure valid output event, using external RESET pulse. Extends to 125 ns when programmed delay
is 100 ns.
19When self-resetting with a full-scale programmed delay.
10Measured from 0.4 V to 2.4 V; source = 1 mA; sink = 4 mA.
11Measured from the data input to the time when the AD9501 becomes 8-bit accurate, after a full-scale change in the program delay data word.
12Measured from the RESET input to the time when the AD9501 becomes 8-bit accurate, after a full-scale programmed delay.
13Supply voltage should remain stable within ± 5% for normal operation.
14Measured at +VS = 5.0 V ± 5%; specification shown is for worst case.
Specifications subject to change without notice.
–2–
REV. B
Share Link: 