AD9501 查看數據表（PDF） - Analog Devices

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AD9501

Digitally Programmable Delay Generator

Analog Devices 

AD9501

NOTES

1Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability

is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.

2Typical thermal impedances: 20-lead plastic leaded chip carrier θJA= 73°C/W; θJC= 29°C/W. 20-pin ceramic DIP θJA= 65°C/W; θJC= 20°C/W. 20-pin plastic DIP

θJA= 65°C/W; θJC= 26°C/W.

3Digital data inputs must remain stable for the specified time prior to the positive transition of the LATCH signal.

4Digital data inputs must remain stable for the specified time after the positive transition of the LATCH signal.

5Programmed delay (tD) = 0 ns. Maximum self-resetting trigger rate is limited to 6.9 MHz with 100 ns programmed delay. If t D= 0 ns and external RESET signal is

used, maximum trigger rate is 23 MHz.

6Programmed delay (tD) = 0 ns. In operation, any programmed delays are in addition to the minimum propagation delay (t PD).

7Programmed delay (tD) = 0 ns. [Minimum propagation delay (tPD)].

8Measured from 50% transition point of the RESET signal input to the 50% transition point of the falling edge of the output.

9Minimum time from the falling edge of RESET to the triggering input to insure valid output pulse, using external RESET pulse.

10Minimum time from triggering event to rising edge of RESET to insure valid output event, using external RESET pulse. Extends to 125 ns when programmed delay

is 100 ns.

11When self-resetting with a full-scale programmed delay.

12Measured from +0.4 V to +2.4 V; source = 1 mA; sink = 4 mA.

13Measured from the data input to the time when the AD9501 becomes 8-bit accurate, after a full-scale change in the program delay data word.

14Measured from the RESET input to the time when the AD9501 becomes 8-bit accurate, after a full-scale programmed delay.

15Supply voltage should remain stable within ± 5% for normal operation.

16Measured at +VS = +5.0 V ± 5%; specification shown is for worst case.

Specifications subject to change without notice.

EXPLANATION OF TEST LEVELS

Test Level

I – 100% production tested.

II – 100% production tested at +25°C, and sample tested at specified

temperatures.

III – Sample tested only.

IV – Parameter is guaranteed by design and characterization testing.

V – Parameter is a typical value only.

VI – All devices are 100% production tested at +25°C. 100% production

tested at temperature extremes for extended temperature devices;

sample tested at temperature extremes for commercial/industrial

devices.

ORDERING GUIDE

Device

Temperature Description

AD9501JN

AD9501JP

AD9501JQ

AD9501SQ

0°C to +70°C

0°C to +70°C

0°C to +70°C

–55°C to +125°C

20-Pin Plastic DIP

20-Lead PLCC

20-Pin Ceramic DIP

20-Pin Ceramic DIP

*N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.

Package

Option*

N-20

P-20A

Q-20

Q-20

DIE LAYOUT AND MECHANICAL INFORMATION

MECHANICAL INFORMATION

Die Dimensions . . . . . . . . . . . . . . . . . . 89 × 153 × 15 (± 2) mils

Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils

Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum

Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground

Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride

Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic

Bond Wire . . . . . . . . 1.25 mil, Aluminum; Ultrasonic Bonding

or 1 mil, Gold; Gold Ball Bonding

REV. A

–3–

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