AD9501 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD9501

Digitally Programmable Delay Generator

Analog Devices 

Ramp charging current and DAC full-scale current are slaved

together in the AD9501 to minimize delay drift over tempera-

ture. To preserve the unit’s low drift performance, both RSET

and CEXT should have low temperature coefficients. Resistors

which are used should be 1% metal film types.

The programmed delay (tD) is set by the DAC inputs, D0–D7.

Graph 1. RC Values vs. Full-Scale Delay Range (tDFS)

AD9501

The minimum delay through the AD9501 corresponds to an

input code of 00H, and FFH gives the full-scale delay. Any

programmed delay can be approximated by:

tD = (DAC code /256) × tDFS

Total delay through the AD9501 for any given DAC code is

equal to:

tTOTAL = tD + tPD

As shown on the block diagram, TTL/CMOS latches are

included to store the digital delay data. Data is latched when

LATCH is HIGH. When LATCH is LOW, the latches are

transparent, and the DAC will attempt to follow any changes on

inputs D0–D7.

The System Timing Diagram, Figure 3, shows the timing

relationship between the input data and the latch. The DAC

settling time (tLD) is approximately 30 ns. After the digital

(Programmed Delay) data is updated, a minimum 30 ns must

elapse between the time LATCH goes high and the arrival of a

TRIGGER pulse to assure rated pulse delay accuracy.

When RESET goes HIGH, the ramp timing capacitor (CEXT +

8.5 pF) is discharged. The RESET input is level-sensitive, and

overrides the TRIGGER input. Therefore, any trigger pulse

which occurs when RESET is HIGH will not produce an output

pulse. As shown on the system timing diagram, Figure 3, the

next trigger pulse should not occur before the Linear Ramp

Settling Time (tLRS) interval is completed to assure rated pulse

delay accuracy.

REV. A

Figure 3. AD9501 System Timing

–7–

Share Link: