XRD64L43 查看數據表（PDF） - Exar Corporation

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XRD64L43

Dual 10-Bit 40MSPS CMOS ADC

Exar Corporation 

Preliminary

XRD64L43

Differential Inputs

The XRD64L43 can be used in either differential or

single-ended input mode. For single-ended inputs, see

the Single-Ended Inputs Section. Differential inputs

reduce system noise by removing noise components

common at both input pins. Figure 5. is a simplified

diagram that is used as a common test circuit with our

XRD64L43ES application board. This circuit is used to

evaluate the dynamic performance of the XRD64L43

using differential inputs. Pin 16, DIFF should be held

high to select differential inputs.

Auto-Calibration

The XRD64L43 incorporates an auto-calibration cir-

cuit which continuously adjusts and matches the

offset and linearity of each ADC. This auto-calibra-

tion circuit is transparent to the user after the initial

4.2ms calibration (168,000 initial clock cycles).

Note: To avoid auto-calibration after power down, do

not disable CKIN. CKIN can be slowed down significantly

to save power without losing calibration.

Input A

Input B

Transformer

22

22

50

Transformer

22

22

50

VINA(+)

VINA(-)

VCMO

VINB(+)

VINB(-)

Figure 5. Common Test Circuit for the

Differential Input Mode

SYNCO, Data Valid Delay and Latency

SYNCO is an output pin provided by the XRD64L43.

Valid data is available on the rising edge of SYNCO,

see Figure 6. The Latency for the XRD64L43 is 17

clock cycles.

CKIN

N

N+1

N+2

Valid Data

SYNCO

N-17

tden=20ns

N-16

N-15

tsynco=2ns (typical)

Figure 6. SYNCO, Data Valid Delay and Latency

for the XRD64L43

Rev. P1.00

11

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