XRT72L52(2001) 查看數據表（PDF） - Exar Corporation

零件编号

产品描述 (功能)

生产厂家

XRT72L52
(Rev.:2001)

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

Exar Corporation 

áç

PRELIMINARY

XRT72L52

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. P1.1.3

Figure 63. Flow Chart depict how to use the LAPD Transmitter ........................................................ 180

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 181

BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 181

4.2.4 The Transmit DS3 Framer Block ........................................................................................................... 181

Figure 64. A Simple Illustration of the Transmit DS3 Framer Block and the associated paths to other Func-

tional Blocks ........................................................................................................................................ 182

TX DS3 CONFIGURATION REGISTER (ADDRESS = 0X30) ........................................................................ 183

TABLE 28: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 7 (TX YELLOW ALARM) WITHIN THE TX DS3 CON-

FIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION .......................... 183

TABLE 29: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 6 (TX X-BITS) WITHIN THE TX DS3 CONFIGURA-

TION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ..................................... 183

TABLE 30: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 5 (TX IDLE) WITHIN THE TX DS3 CONFIGURATION

REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER ACTION .......................................................... 184

TABLE 31: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 4 (TX AIS PATTERN) WITHIN THE TX DS3 CON-

FIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION .......................... 184

TABLE 32: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (TX LOS) WITHIN THE TX DS3 CONFIGURATION

REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ............................................. 185

TX DS3 M-BIT MASK REGISTER, ADDRESS = 0X35 ............................................................................... 185

TX DS3 F-BIT MASK1 REGISTER, ADDRESS = 0X36 .............................................................................. 186

TX DS3 F-BIT MASK2 REGISTER, ADDRESS = 0X37 .............................................................................. 186

TX DS3 F-BIT MASK3 REGISTER, ADDRESS = 0X38 .............................................................................. 186

TX DS3 F-BIT MASK4 REGISTER, ADDRESS = 0X39 .............................................................................. 186

4.2.5 The Transmit DS3 Line Interface Block ................................................................................................. 186

Figure 65. Approach to Interfacing the XRT72L52 Framer IC to the XRT7302 DS3/E3/STS-1 Transmitter

LIU (one channel shown) .................................................................................................................... 187

Figure 66. A Simple Illustration of the Transmit DS3 LIU Interface block .......................................... 188

Figure 67. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit DS3

LIU Interface is operating in the Unipolar Mode .................................................................................. 188

I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 189

TABLE 33: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O CON-

TROL REGISTER AND THE TRANSMIT DS3 FRAMER LINE INTERFACE OUTPUT MODE ................................ 189

Figure 68. Illustration of AMI Line Code ............................................................................................. 190

Figure 69. Illustration of two examples of B3ZS Encoding ................................................................. 190

I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 191

TABLE 34: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE I/O CONTROL REGISTER AND THE BI-

POLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT DS3 LIU INTERFACE BLOCK ................................. 191

II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 191

TABLE 35: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL

REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................... 191

Figure 70. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG

are configured to be updated on the rising edge of TxLineClk ............................................................ 192

Figure 71. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG

are configured to be updated on the falling edge of TxLineClk ........................................................... 192

4.2.6 Transmit Section Interrupt Processing .................................................................................................. 192

BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ..................................................................... 193

TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) .................................. 193

TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) .................................. 194

TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ................................................... 194

TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ................................................... 195

4.3 THE RECEIVE SECTION OF THE XRT72L52 (DS3 MODE OPERATION) ................................................................. 195

Figure 72. A Simple Illustration of the Receive Section of the XRT72L52, when it has been configured to

operate in the DS3 Mode .................................................................................................................... 195

4.3.1 The Receive DS3 LIU Interface Block ................................................................................................... 195

Figure 73. A Simple Illustration of the Receive DS3 LIU Interface Block ........................................... 196

Figure 74. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data

VII

Share Link: