XRT91L31 查看數據表（PDF） - Exar Corporation

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XRT91L31

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

Exar Corporation 

REV. 1.0.2

PIN DESCRIPTION

NAME

CDRREFSEL

LEVEL

LVTTL,

LVCMOS

TYPE

I

LOOPTIME

LVTTL,

I

LVCMOS

CDRDIS

LVTTL,

I

LVCMOS

XRT91L31

STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER

PIN

DESCRIPTION

60 Clock and Data Recover Unit Reference Frequency Select

Selects the Clock and Data Recovery Unit reference frequency

based on the table below.

"Low" = CDR uses CMU’s reference clock

"High" = CDR reference clock from CDRAUXREF-

CLK

CDRREF-

SEL

0

1

1

STS12/ CDRAUXREF-

STS3 CLK Frequency

Data Rate

CDR uses CMU’s reference clock

(see CMUFREQSEL pin)

0

77.76 MHz

STS-3/STM-1

155.52 Mbps

1

77.76 MHz STS-12/STM-4

622.08 Mbps

NOTE: CDRAUXREFCLK requires accuracy of 77.76 MHz

+−200 ppm.

2

Loop Timing Mode

When the loop timing mode is activated the external reference

clock to the input of the Retimer is replaced with the high-speed

recovered receive clock from the CDR.

"Low" = Disabled

"High" = Loop timing Activated

12 Clock and Data Recovery Unit Disable

Active "High." Disables internal Clock and Data Recovery unit.

Received serial data bypasses the integrated CDR block.

RXINP/N is then sampled on the rising edge of externally

recovered differential clock XRXCLKIP/N coming from the opti-

cal module.

"Low" = Internal CDR unit is Enabled

"High" = Internal CDR unit is Disabled and Bypassed

7

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